JPH0319575B2 - - Google Patents

Info

Publication number
JPH0319575B2
JPH0319575B2 JP59003347A JP334784A JPH0319575B2 JP H0319575 B2 JPH0319575 B2 JP H0319575B2 JP 59003347 A JP59003347 A JP 59003347A JP 334784 A JP334784 A JP 334784A JP H0319575 B2 JPH0319575 B2 JP H0319575B2
Authority
JP
Japan
Prior art keywords
data
buffer memory
host computer
ram buffer
peripheral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59003347A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59167767A (ja
Inventor
Bui Shesu Jeishu
Jei Mootensen Deibitsudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Publication of JPS59167767A publication Critical patent/JPS59167767A/ja
Publication of JPH0319575B2 publication Critical patent/JPH0319575B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Information Transfer Systems (AREA)
JP59003347A 1983-01-11 1984-01-10 バ−ストモ−ドデ−タブロツク転送システム Granted JPS59167767A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US457178 1983-01-11
US06/457,178 US4542457A (en) 1983-01-11 1983-01-11 Burst mode data block transfer system

Publications (2)

Publication Number Publication Date
JPS59167767A JPS59167767A (ja) 1984-09-21
JPH0319575B2 true JPH0319575B2 (en]) 1991-03-15

Family

ID=23815745

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59003347A Granted JPS59167767A (ja) 1983-01-11 1984-01-10 バ−ストモ−ドデ−タブロツク転送システム

Country Status (4)

Country Link
US (1) US4542457A (en])
EP (1) EP0113683B1 (en])
JP (1) JPS59167767A (en])
DE (1) DE3480961D1 (en])

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4644463A (en) * 1982-12-07 1987-02-17 Burroughs Corporation System for regulating data transfer operations
US4616337A (en) * 1983-03-30 1986-10-07 Burroughs Corporation Automatic read system for peripheral-controller
US4534013A (en) * 1983-06-30 1985-08-06 Burroughs Corporation Automatic write system for peripheral-controller
US4868742A (en) * 1984-06-20 1989-09-19 Convex Computer Corporation Input/output bus for system which generates a new header parcel when an interrupted data block transfer between a computer and peripherals is resumed
US5151999A (en) * 1986-03-31 1992-09-29 Wang Laboratories, Inc. Serial communications controller for transfer of successive data frames with storage of supplemental data and word counts
US4942515A (en) * 1986-03-31 1990-07-17 Wang Laboratories, Inc. Serial communications controller with FIFO register for storing supplemental data and counter for counting number of words within each transferred frame
US4821185A (en) * 1986-05-19 1989-04-11 American Telephone And Telegraph Company I/O interface system using plural buffers sized smaller than non-overlapping contiguous computer memory portions dedicated to each buffer
US4975829A (en) * 1986-09-22 1990-12-04 At&T Bell Laboratories Communication interface protocol
US5142628A (en) * 1986-12-26 1992-08-25 Hitachi, Ltd. Microcomputer system for communication
US4959771A (en) * 1987-04-10 1990-09-25 Prime Computer, Inc. Write buffer for a digital processing system
US5081701A (en) * 1987-04-20 1992-01-14 Tandem Computers Incorporated System for controlling data transfer using transfer handshake protocol using transfer complete and transfer inhibit signals
WO1988009017A1 (fr) * 1987-05-06 1988-11-17 Fujitsu Ten Limited Procede et dispositif de transfert de donnees
US4864532A (en) * 1987-09-21 1989-09-05 Unisys Corporation Small computer systems interface--data link processor
US4905184A (en) * 1987-09-21 1990-02-27 Unisys Corporation Address control system for segmented buffer memory
US5133054A (en) * 1987-10-20 1992-07-21 Sharp Kabushiki Kaisha Data transmission apparatus for autonomously and selectively transmitting data to a plurality of transfer path
US4891784A (en) * 1988-01-08 1990-01-02 Hewlett-Packard Company High capacity tape drive transparently writes and reads large packets of blocked data between interblock gaps
US5210851A (en) * 1988-01-08 1993-05-11 Hewlett-Packard Company High capacity tape drive transparently writes and reads large packets of blocked data between interblock gaps
US5121479A (en) * 1988-01-27 1992-06-09 Storage Technology Corporation Early start mode data transfer apparatus
US5625842A (en) * 1988-05-18 1997-04-29 Zilog, Inc. System for the automatic transfer of message status in digital data communication
US4888727A (en) * 1989-01-10 1989-12-19 Bull Hn Information Systems Inc. Peripheral controller with paged data buffer management
US5237676A (en) * 1989-01-13 1993-08-17 International Business Machines Corp. High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device
US5347637A (en) * 1989-08-08 1994-09-13 Cray Research, Inc. Modular input/output system for supercomputers
US5274795A (en) * 1989-08-18 1993-12-28 Schlumberger Technology Corporation Peripheral I/O bus and programmable bus interface for computer data acquisition
US5170477A (en) * 1989-10-31 1992-12-08 Ibm Corporation Odd boundary address aligned direct memory acess device and method
GB9018993D0 (en) * 1990-08-31 1990-10-17 Ncr Co Work station interfacing means having burst mode capability
WO1992009074A1 (en) * 1990-11-13 1992-05-29 Wangtek, Inc. System and method of controlling data transfer rate in a magnetic tape drive
CA2065989C (en) * 1991-06-07 1998-03-31 Don Steven Keener Personal computer data flow control
US5640599A (en) * 1991-12-30 1997-06-17 Apple Computer, Inc. Interconnect system initiating data transfer over launch bus at source's clock speed and transfering data over data path at receiver's clock speed
US5887196A (en) * 1991-12-30 1999-03-23 Apple Computer, Inc. System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer
US5450546A (en) * 1992-01-31 1995-09-12 Adaptec, Inc. Intelligent hardware for automatically controlling buffer memory storage space in a disk drive
JPH06214897A (ja) * 1992-12-14 1994-08-05 E Syst Inc 誤り状態検出時に周辺装置に記憶したデータの損失を最少にする方法
US5461701A (en) * 1992-12-18 1995-10-24 Microsoft Corporation System and method for peripheral data transfer
US5499384A (en) * 1992-12-31 1996-03-12 Seiko Epson Corporation Input output control unit having dedicated paths for controlling the input and output of data between host processor and external device
JP2621772B2 (ja) * 1993-10-29 1997-06-18 日本電気株式会社 シリアル伝送装置
US5517615A (en) * 1994-08-15 1996-05-14 Unisys Corporation Multi-channel integrity checking data transfer system for controlling different size data block transfers with on-the-fly checkout of each word and data block transferred
JP3078204B2 (ja) * 1995-06-01 2000-08-21 株式会社東芝 磁気ディスク装置及び磁気ディスク装置におけるバッファ管理方法
US6470405B2 (en) * 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
JP2970513B2 (ja) * 1996-01-30 1999-11-02 日本電気株式会社 半導体記憶装置およびその制御方法
US20050177660A1 (en) * 2004-02-05 2005-08-11 Rajesh Mamidwar Method and system for merged rate-smoothing buffer with burst buffer

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4040026A (en) * 1974-05-08 1977-08-02 Francois Gernelle Channel for exchanging information between a computer and rapid peripheral units
US4040037A (en) * 1976-06-01 1977-08-02 International Business Machines Corporation Buffer chaining
US4162520A (en) * 1976-09-30 1979-07-24 Burroughs Corporation Intelligent input-output interface control unit for input-output subsystem
US4228501A (en) * 1978-06-21 1980-10-14 Data General Corporation Data transfer technique for use with peripheral storage devices
US4371932A (en) * 1979-07-30 1983-02-01 International Business Machines Corp. I/O Controller for transferring data between a host processor and multiple I/O units
US4293928A (en) * 1979-12-14 1981-10-06 Burroughs Corporation Peripheral dependent circuit for peripheral controller
US4445176A (en) * 1979-12-28 1984-04-24 International Business Machines Corporation Block transfers of information in data processing networks
US4357681A (en) * 1980-05-07 1982-11-02 Burroughs Corporation Line turn circuit for data link
JPS5939768B2 (ja) * 1980-10-01 1984-09-26 富士通株式会社 入出力システム
JPS5762438A (en) * 1980-10-03 1982-04-15 Toshiba Corp Control system for fifo memory
JPS57113162A (en) * 1980-12-29 1982-07-14 Fujitsu Ltd High-speed external storage device
JPS57123537U (en]) * 1980-12-29 1982-08-02
JPS57120144A (en) * 1981-01-16 1982-07-27 Toshiba Corp Data transfer system
US4393445A (en) * 1981-03-06 1983-07-12 International Business Machines Corporation Information-signal recording apparatus employing record volume oriented identification signals
US4413319A (en) * 1981-03-09 1983-11-01 Allen-Bradley Company Programmable controller for executing block transfer with remote I/O interface racks
US4420819A (en) * 1981-03-13 1983-12-13 Data Card Corporation System for processing and storing transaction data and for transmitting the transaction data to a remote host computer
DE3382684T2 (de) * 1982-11-16 1993-08-26 Unisys Corp Blockzaehlersystem zur ueberwachung des datentransfers.

Also Published As

Publication number Publication date
EP0113683A3 (en) 1986-10-15
EP0113683B1 (en) 1990-01-03
US4542457A (en) 1985-09-17
DE3480961D1 (de) 1990-02-08
EP0113683A2 (en) 1984-07-18
JPS59167767A (ja) 1984-09-21

Similar Documents

Publication Publication Date Title
JPH0319575B2 (en])
US4644463A (en) System for regulating data transfer operations
US4607348A (en) Transfer rate control system from tape peripheral to buffer memory of peripheral controller
US4602331A (en) Magnetic tape-data link processor providing automatic data transfer
EP0241129B1 (en) Addressing arrangement for a RAM buffer controller
US5133062A (en) RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory
US4467447A (en) Information transferring apparatus
CA1318037C (en) Data processing system bus architecture
US5301279A (en) Apparatus for conditioning priority arbitration
US4041473A (en) Computer input/output control apparatus
CA1246748A (en) Dual function i/o controller
JPH0332094B2 (en])
JPH0562382B2 (en])
US6003122A (en) Direct memory access controller
US4616337A (en) Automatic read system for peripheral-controller
US4613954A (en) Block counter system to monitor data transfers
US4534013A (en) Automatic write system for peripheral-controller
EP0316020B1 (en) Block counter system to monitor data transfers
JPS6148745B2 (en])
EP0117682B1 (en) Peripherally synchronized data transfer system
CA1211573A (en) System for regulating data transfer operations